Compress Verilog Guide
Tuesday, 3 October 2017، 04:11 AM
Hi, in this post i will upload a pdf file which i have written as a guide to verilog programming.
Note that this guide is useful for a person who has some experience with verilog and wants to remember important functions and techniques in verilog in order to write verilog programs for FPGA and other hardwares.
all of contents include examples.
List of contents:
- variables
- concat and replicate
- operators
- module and test bench (with examples)
- port binding
- blocking and non-blocking assignment
- clock generate
- initial and always block (parallel blocks)
- combinational logic design
- reduction operators
- state machines
DOWNLOAD FULL VERSION IN PDF FORMAT HERE
DEMO:
============================
VERILOG GUIDE
by NAVID MALEK
nmalek@ce.sharif.edu
============================
variables in verilog:
-reg (can have vector identity)
-integer
-real
-time,realtime
assignment: beceause they are not wires, they should be assigned only in sequential blocks(always,initial,task,funcion)
read: can be read anywhere (i.e. a driver for a wire)
--------------------------------------------------------------------------
variables and wires default is X
--------------------------------------------------------------------------
integer : 32bit int-default is X
real : 64bit floating point-default is 0.0
ONLY used in test bench
--------------------------------------------------------------------------
time variable:
time my_time;
my_time =$time;// get current time of simulation
-------------------------------------------------
vector:
e.g.
reg [3:0]A = 3'b 1001;
array:
e.g.
reg A[3:0] = 3'b 1001;
------------------------------------------------------------
multi-dementional wire and reg:
e.g.
reg [7:0] var [1:10][1:100];
reg [7:0] mem [1023:0];
--------------------------------------------------
a value is considered as X if all bits are 0 and X or 0 and Z or 0 and x and z
